Recently, the demand is ever increasing for digital electronic equipment to handle a larger amount of information processing. To meet such a demand, the signal speed is increasing in the equipment, and the transmission margin is being reduced.
In keeping with such a trend, there is a need to estimate a transmission margin with good accuracy by comprehensively estimating a large number of factors that cause deterioration of the transmission margin.
The related art includes a simulation apparatus, a transmission waveform analysis apparatus, and a digital circuit noise analysis method. The simulation apparatus is for virtual design use to find the optimal component layout in a circuit. The transmission waveform analysis apparatus is for estimation of the influence of signal deterioration caused by circuit components in a transmission circuit that performs high-speed serial transmission of digital signals. The digital circuit noise analysis method can complete calculation in a short time. Examples include Japanese Laid-open Patent Publication No. 2005-63070, Japanese Laid-open Patent Publication No. 2004-287738, and Japanese Laid-open Patent Publication No. 2001-265848.
The problem with such related art is that, because no method has been yet proposed to estimate a transmission margin in a fixed manner, the transmission margin has been calculated in various different manners by people in various different fields in charge of design. The resulting calculated transmission margins thus vary in accuracy depending on the personal knowledge and understanding of the field.
There is another problem that a circuit simulation, e.g., HSPICE™, model does not accurately represent component variations, and thus is not capable of accurately evaluating a risk of causing a failure in volume production due to the component variations.
Moreover, obtaining such a circuit simulation model requires a complicated procedure such as concluding an NDA (Non-Disclosure Agreement), for example.